Generally, a non-volatile semiconductor memory device using a single-layer polysilicon may include a large-area capacitor using a well as a control gate, a MOS (Metal-Oxide-Semiconductor) transistor for data reading (hereinafter merely referred to as a read transistor) as constituent elements. Conventionally, the non-volatile semiconductor memory device has had another capacitor added thereto to further add an erasure function thereto.
National Publication of International Patent Application. No. 2009-538519 (hereinafter referred to as Patent Literature 1) is an example of the non-volatile semiconductor memory device, in which a PMOS (P-channel MOS) access transistor is provided as a read transistor, and a current flowing through the read transistor is detected during a data reading operation so that it can be determined whether data is programmed to or erased from a corresponding floating gate. In Patent Literature 1, during data erasure operation, a high voltage drop is generated between both ends of a gate insulating film of the read transistor, and charge is elected from the floating gate via the gate insulating film of the read transistor so that data can be erased from a memory cell.
Furthermore, Patent Literature 1 also discloses a configuration in which an NMOS (N-channel MOS) access transistor is provided as a read transistor, charge is tunneled, into the floating gate from a channel of the read transistor when data is programmed to the floating gate, and the data is programmed to the floating gate as another example.
However, generally in an area of the gate insulating film through which the charge has passed, a charge passage region is damaged by an applied electric field to or hot-carrier stress on the gate insulating film. Therefore, in a conventional read transistor in which charge passes through a gate insulating film during data programming and erasure operations, the gate insulating film is damaged. A reading current obtained from the read transistor decreases due to interface state generation, for example, so that a malfunction of the read transistor may occur.
When the read transistor is used for data programming, like in Patent Literature 1, a part of the charge may be injected into a sidewall region of the read transistor, for example. The charge in the sidewall region is difficult to remove. In the read transistor, a threshold voltage (a voltage at the time when the read transistor is switched from off to on, which is referred to as Vth) is shifted by repetition of data programming so that a malfunction of the read transistor may occur.
As a configuration for solving such a problem, a configuration in which a read transistor is not used as a charge transfer path during data programming and erasure is considered. In this case, a configuration in which a programming bit line and a reading bit line for determining selection/non-selection of programming are independently provided, and the bit lines prevent a read transistor region from serving as a charge transfer path during data programming and erasure can be implemented, like in a non-volatile semiconductor memory device discussed in Japanese Patent Laid-Open No. 2005-175411 (hereinafter referred to as Patent Literature 2).